Traditional metal oxide semiconductor field effect transistor (MOSFET) fabrication techniques include process flows for constructing planar transistors. With planar transistors, transistor density can be increased by decreasing the pitch between transistor gate elements. With planar transistors, however, the ability to decrease gate pitch is fundamentally limited by the required gate length and spacer thickness. Moreover, as transistor size requirements in integrated circuits (ICs) continue to decrease, power supply voltages and threshold voltages are also decreasing. Lower threshold voltages can be difficult to obtain in conventional MOSFETs because, as the threshold voltage is reduced, the ratio of ON-current to OFF-current may also decrease. ON-current refers to the current through a MOSFET when a gate voltage is above the threshold voltage and can be as high as the supply voltage, while OFF-current refers to current through a MOSFET when the gate voltage is below the threshold voltage and can approach or equal zero volts.
Considerable research has been devoted to the development of nonplanar transistor architectures. Some non-planar transistor architectures, such as nanoribbon transistors, nanosheet transistors, and nanowire transistors, employ semiconductor channels with gate-all-around (GAA) technologies to achieve increased device density, greater power efficiency, and some increased performance over lateral devices. In a nanoribbon transistor, the gate stack wraps around the full perimeter of each nanoribbon, enabling fuller depletion in the channel region, and reducing short-channel effects due to a steeper subthreshold swing (SS) and a smaller drain induced barrier lowering (DIBL).